Modern semiconductor fabrication involves numerous steps including photolithography, material deposition, and etching to form a plurality of individual semiconductor devices or integrated circuit chips (dice) on a single semiconductor silicon wafer. Typical semiconductor wafers produced today may be at least about 6 inches or more in diameter, with a 12 inch diameter wafer being one common size. Some of the individual chips formed on the wafer, however, may have defects due to variances and problems that may arise during the intricate semiconductor fabrication process. Prior to wafer dicing wherein the individual integrated circuit chips (dies) are separated from the semiconductor wafer, electrical performance and reliability tests are performed on a plurality of chips simultaneously by energizing them for a predetermined period of time (i.e., wafer level burn-in testing). These tests may typically include LVS (layout versus schematic) verification, IDDq testing, etc. The resulting electrical signals generated from each chip or DUT (device under test) are captured and analyzed by automatic test equipment (ATE) having test circuitry to determine if a chip has a defect.
To facilitate wafer level burn-in testing and electrical signal capture from numerous chips on the wafer at the same time, DUT boards or probe cards as they are commonly known in the art are used. Probe cards are essentially printed circuit boards (PCBs) that contain a plurality of metallic electrical probes that mate with a plurality of corresponding electrical contacts or terminal formed on the wafer for the semiconductor chips. Each chip or die has a plurality of contacts or terminals itself which must each be accessed for testing. A typical wafer level test will therefore require that electrical connection be made between well over 1,000 chip contacts or terminals and the ATE test circuitry. Accordingly, precisely aligning the multitude of probe card contacts with chip contacts on the wafer and forming sound electrical connections is important for conducting accurate wafer level testing. Probe cards are typically mounted in the ATE and serve as an interface between the chips or DUTs and the test head of the ATE.
As semiconductor fabrication technology advances continue to be implemented, the critical dimension or spacing between electrical test contact pads and bumps (i.e. “pitch”) of dies or chips on the semiconductor wafer continues to shrink. The present major trend in semiconductor fabrication is moving towards 3D IC chip packages with heterogeneous chip stacking. Such 3D IC chip packages include DUTs having a TSV (through silicon via) electrical interconnect structure with corresponding micro bump testing contact fine pitch arrays with a micro bump pitch of less than 50 microns (μm).
A technology bottleneck occurs that is associated with existing known testing probe card designs and assembly techniques that do not readily support such small testing pad micro bump pitches as encountered on 3D IC chip packages. There are limitations associated with existing guide plate manufacturing having closely spaced holes which support small diameter (e.g. 25 microns) needle-like metal testing probe which are flexible and easily bent, guide plate assembly techniques, and probe handling required to manually insert the slender probes through small diameter probe holes (e.g. 30 microns) in the guide plates which is a time-consuming operation and results in all too frequent damage to the structurally thin and weak probes.
An improved testing probe card and method for fabricating the same is therefore desired.
All drawings are schematic and are not drawn to scale.